Senior Designer - System Architecture Team

System Level Designer / ArchitectYou will be part of an R&D team developing >100Gbps NRZ and PAM4 serial-link transceivers. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross-functional design team of analog and digital designers, and hardware engineers.You will be involved in all stages of development including:Architecture: definition of architecture and specifications for the transmitter and receiverModelling: design and maintenance of the system level modelSign-off: system level simulation of the design performance across multiple protocols and channelsSilicon: qualification and correlation of performance and algorithms in siliconCustomers: assisting customers on system level performance and algorithmic issuesYou have a PhD in Electrical or Computer Engineering.Due to the cross-disciplinary nature of this position, key qualifications include one or more of the following:Modelling - experience in C/Matlab modeling of circuits and systemsDigital – experience with DSPCommunications theory – equalization, coding, noise/crosstalk filteringBeneficial Experience:Experience in analyzing link budgets for either NRZ and PAM4 high-speed serial linksFamiliarity with modelling of SERDES transmitters and receivers in Matlab or similar toolKnowledge of circuit topologies in high-speed Rx/Tx SerDes PHYUnderstanding of Tx/Rx equalization techniques.Knowledge of CDR architectures and CDR loop dynamicsKnowledge about common high-speed serial data protocols including Ethernet, OIFExperience in lab testing of high-speed serial links #J-18808-Ljbffr